Intel's Wireless Communication Solutions (WCS) Group, is a world-class leader in wireless connectivity and the industry's #1 provider of PC, WIFI and BT solutions.
Join our newly emerging scan team!

What you will do?

You will be responsible for scan architecture and design scan clock definitions, RTL validation, ATPG, GLS, timing analysis and post-Si activity support.

You will be leading execution of DFT activities and take part in setting new DFT methodologies and leading edge techniques.

We work with standard tools and flows such as Tessent and SpyG.

We design ASICs for all TIER1 foundries such as TSMC, GF etc.

Qualifications:
What we are looking for?

An experienced DFT Engineer, with at least 3 years experience in SCAN.

Strong leadership in driving execution across different teams

BSc/MSc in Electrical Engineering

Experience in RTL design and GLS

Experience in scan debug and pattern generation

Knowledge in clocking and timing analysis

Preferred Qualifications

Design automation skills and scripting proficiency

Experience in design verification and post-Si implementation